A packet switching device consists of Switch Access (SA) chips and Switch Fabric (SF) chips on a line card. In a high-capacity packet switching system, switching chips consist of two levels of chips: upper-level SF2 chips and lower-level SF1 chips, and in an intermediate-capacity or low-capacity switching system, switching chips merely consist of SA chips and SF2 chips. FIG. 1 shows the structure of a global synchronization network. In a distributed packet switching device, all line cards need to be synchronized in timestamp counting, so as to ensure that data packets simultaneously sent from all line cards have the same timestamp so that the data packets can be recombined at the position of a downstream destination line card.
In an existing global synchronization method, a reference is basically selected in a software-designated manner in which each chip in a packet switching system reports its own state and the state of a serdes link to a uniform network manager, the network manager conducts an operation to determine which chip should be designated as a reference, and thereby conducts a calculation to determine which link each chip should select as a calibration source, and then successively configures the commands in each chip in this system. The foregoing processes need to be carried out again when any link or chip in the system malfunctions. The foregoing calculation method is complicated and the state collection and command issuing process is long, especially when there are thousands of chips in a large-scale packet switching system. It takes a very long time to reselect a new reference when a link or chip in the system malfunctions, which may lead to the loss of a packet in the system or congestion resulting from out of alignment of time.
In contrast, since the reselection and synchronization of a reference can be completed in a short time for the separate operation of each chip, the disclosure based on a pure-hardware operation greatly reduces the possibility of occurrence of packet loss or congestion when a link or chip in a system malfunctions.